Embodiments of the present invention relate to closed loop voltage control with adaptive on time control schemes. A preferred embodiment of the invention is intended for use in a DC-DC switching regulator circuit, but the circuit may also be used in other applications that require closed loop voltage regulation.
Referring to FIGS. 1 and 2A, there is a DC-DC switching regulator circuit of the prior art as disclosed by Tateishi et al. in U.S. Pat. No. 7,595,624. The switching regulator includes a pulse-width modulation (PWM) controller 52 configured to alternately activate 10 a high-side transistor 54 and a low-side transistor 56 as shown at FIG. 1. The PWM controller 52 controls the duty cycle of pulses provided to both transistors 54 and 56. Transistor 54 has a drain terminal that is connected to a supply voltage source VDD. Transistor 56 has a source terminal connected to ground. Transistors 54 and 56 have a common terminal that produces switching voltage VSW. An inductor 60 is interconnected between the common terminal and an output terminal producing a voltage VOUT. A freewheeling diode 62 is interconnected between one terminal of inductor 60 and ground.
During an on-time, controller 52 activates transistor 54 while transistor 56 remains inactive. When transistor 54 is on, voltage VSW increases to approximately VDD. Consequently, current through inductor 60 increases. During an off-time, the controller 52 deactivates transistor 54 and activates transistor 56. Consequently, voltage VSW decreases to approximately ground. Current through inductor 60, however, tends to remain unchanged. Thus, the voltage VSW becomes negative relative to ground so that inductor current is supplied through the freewheeling diode 62. Accordingly, the switching regulator operates to maintain the current flow through inductor 60, thus providing an output voltage VOUT across a load capacitor 64 and a load resistor 66.
The switching regulator also includes a PWM comparison circuit 68-1 to determine the off-time relative and the on-time of transistor 54. The output voltage VOUT is applied to the PWM comparison circuit through a voltage divider 70 that includes resistors R1 and R2. The voltage divider provides a feedback voltage VFB as an output. The PWM comparison circuit includes a ramp signal generator 72-1 configured to generate a ramp signal, preferably by alternately charging or discharging a capacitor. The feedback voltage VFB and the ramp signal are added together by adder 74-1. A resultant modified feedback voltage VFB2 is provided to a comparator or error amplifier 76, which compares the modified feedback voltage VFB2 and the reference voltage VREF. The comparator 76 thus provides an output to the PWM controller 52 to switch between the on-time and the off-time. In this manner, on-time (TON) is approximately equal to the switching time (TSW=TON+TOFF) multiplied by VOUT/VDD, where the switching regulator frequency is equal to 1/TSW.
As the operating frequency of the switching regulator circuit of FIG. 2A increases, several problems limit circuit efficiency. Due to noise or other effects, reference voltage VREF can be subject to error such that output voltage VOUT is compared to VREF, thereby producing error voltage VE as shown at FIG. 2A. This error voltage produces a next on-time error T0 and a premature output ripple voltage 12. Tateishi et al. disclose an improvement as shown at FIG. 2B. There, the maximum feedback voltage VFB is added to reference voltage VR to produce modified feedback voltage VFB2. The relatively steeper slope of VFB2 decreases the uncertainty on-time from TUNC1 to TUNC2.
The circuit of FIG. 2A was subsequently improved with the addition of the current sense circuit of FIG. 3A connected in parallel with inductor 60 as disclosed by Texas Instruments Inc., Application Report SLVA453-February 2011. The current sense circuit includes series-connected resistor 300 and capacitor 302 in parallel with inductor 60 and produces positive current sense signal CSP. Series-connected resistor 304 and capacitor 306 are connected in parallel with capacitor 302 and produce negative current sense signal CSN.
Referring now to FIG. 3B, there is a timing diagram showing operation of the current sense circuit of FIG. 3A in continuous current mode (CCM). Here, CCM means that either transistor 54 or 56 (FIG. 2A) is always on. At time t1 transistor 54 is activated and voltage VSW goes high. Responsively, voltage CSP emulates the inductor current IL until transistor 54 is turned off and transistor 56 is turned on. At time t2, CSP again emulates inductor current IL and goes low to a valley at time t3. CSN, however, has an intermediate value between the peak and valley of CSP.
Referring next to FIG. 3C, there is a timing diagram showing operation of the current sense circuit of FIG. 3A in discontinuous current mode (DCM). Here, DCM means that either transistor 54 or 56 (FIG. 2A) is on or both are off. At time t1 transistor 54 is activated and voltage VSW goes high. Voltage CSP again emulates the inductor current IL until transistor 54 is turned off and transistor 56 is turned on. At time t2, CSP again emulates inductor current IL and decreases until time t3 when transistor 56 is turned off. Between times t3 and t4, both transistors 54 and 56 are off, inductor current IL is zero, and CSP and CSN vary as capacitors 302 and 306 discharge. The offset of CSN in CCM and DCM, is not constant and is, therefore, difficult to cancel when compared to CSP. Various embodiments of the present invention are directed to solving these problems and improving operation of the switching regulator.